1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage apparatus such as a flash memory having a floating gate and a control gate to which positive and negative voltages are applied during a memory cell operation.
2. Description of the Related Art
FIG. 15 to FIG. 17 schematically show a conventional nonvolatile semiconductor storage apparatus of this type. FIG. 17 is a plan view showing the conventional nonvolatile semiconductor storage apparatus. FIG. 15 is a cross sectional view along the line A-Axe2x80x2 in FIG. 17, and FIG. 16 is a cross sectional view along the line B-Bxe2x80x2 in FIG. 17. Explanation will be given on this conventional nonvolatile semiconductor storage apparatus with reference to these drawings.
In a P-type semiconductor substrate 1, there is formed an N-type well 2 to oppose to the P-type semiconductor substrate 1. In the N-type well 2, there is formed a P-type well 3 to oppose to the N-type well 2.
In a P-type semiconductor substrate 1, there is formed an N-type well 2 to oppose to the P-type semiconductor substrate 1. In the N-type well 2, there is formed a P-type well 3 to oppose to the N-type well 2. The P-type well 3 has a main surface on which a composite gate 8 is formed. The composite gate 8 consists of a first gate insulation film 4, a floating gate 5, a second gate insulation film 6, and a control gate 7 which are successively layered. On a surface of the P-type well 3 adjacent to the composite gate 8, a source 10 and a drain 11 are formed by an N+ -diffused layer. Moreover, over a part of the P-type well 3, there are formed a first inter-layer insulation film 12 and a contact 13, over which a first metal wiring 14, a second inter-layer insulation film 15, a second metal wiring 16, and a cover film 17 are formed.
Moreover, it is known that by connecting the control gate 7 to a diode through a wiring layer, it is possible to prevent a charge-up during an etching. However, in this type of nonvolatile semiconductor storage apparatus, both positive and negative voltages are applied to the control gate 7 during a memory cell operation. Accordingly, it is impossible to connect the control gate 7 to a charge-up preventing diode. Consequently, a charge-up is inevitable for a memory cell having the floating gate 5.
The conventional technology has a problem that a charge-up during wiring layer etching causes a memory cell floating gate to trap an electron or hole, causing characteristic fluctuation and an insulation film reliability lowering or insulation destruction. This is because both positive and negative voltages are applied to the control gate during a memory cell operation and the control gate cannot be connected to a charge-up preventing diode. That is, if a charge-up preventing diode is connected to the control gate, the charge-up preventing diode is biased in a forward direction by either positive or negative voltage applied and accordingly, it becomes impossible to apply a desired voltage to the control gate.
It is therefore an object of the present invention to provide a nonvolatile semiconductor storage apparatus having a floating gate and a control gate to which both positive and negative voltages are applied during a memory cell operation, which apparatus enables to prevent characteristic fluctuation and insulation film reliability lowering or insulation destruction due to charge-up during a wiring layer etching.
The nonvolatile semiconductor storage apparatus according to the invention is an improved nonvolatile semiconductor storage apparatus having a floating gate and a control gate on a semiconductor substrate. The nonvolatile semiconductor storage apparatus according to an embodiment of the present invention is characterized in that a first well of a second conductive type opposite to the first conductive type of the semiconductor substrate is formed on the semiconductor substrate, and in the first well is formed a semiconductor layer of the first conductive type, which semiconductor layer is electrically connected to the control gate.
The nonvolatile semiconductor storage apparatus according to a further embodiment of the present invention is characterized in that on the semiconductor substrate of a first conductive type is formed a first well of a second conductive type opposite to the first conductive type of the semiconductor substrate, and in the first well is formed a second well of the first conductive type, in which is formed a semiconductor layer of the second conductive type, which semiconductor layer is electrically connected to the control gate. That is, a first well of an opposite conductive type to the semiconductor substrate is formed on the semiconductor substrate. A second well of an opposite conductive type to the first well is formed in the first well, and a semiconductor layer of an opposite conductive type to the second well is formed in the second well. This semiconductor layer is connected to the memory cell control gate so as to realize a charge-up preventing element.
The nonvolatile semiconductor storage apparatus production method according to the present invention is an improved production method for producing a nonvolatile semiconductor storage apparatus having a floating gate and a control gate on a semiconductor substrate. The production method according to an embodiment is characterized by steps of: forming on the semiconductor substrate of a first conductive type, a semiconductor layer of a second conductive type opposite to the first conductive type; electrically connecting the semiconductor layer to the control gate, and electrically insulating the semiconductor layer from the control gate during or after a wiring layer etching.
The nonvolatile semiconductor storage apparatus production method according to a further embodiment is characterized by steps of: forming on the semiconductor substrate of a first conductive type, a semiconductor layer of a second conductive type opposite to the first conductive type; electrically connecting the semiconductor layer to the control gate using a wiring, and cutting off the wiring connecting the semiconductor layer to the control gate during or after a wiring layer etching. In other words, the memory cell control gate is connected to the charge-up preventing diode and during a final wiring layer etching, the control gate is cut off from the charge-up preventing diode.
According to the present invention, the charge-up preventing element for preventing charge-up during a wiring layer etching assures an electric flow path, enabling to prevent a charge-up which may cause a memory cell characteristic fluctuation and an insulation film reliability lowering or insulation destruction as well as to enable to apply both of positive and negative voltages during a cell operation.
More specifically, an N-type well is formed on a P-type substrate. In the N-type well is formed a P-type well. In the P-type well, a N+ diffusion layer is formed. This N+ diffusion layer is connected to the control gate, whereas the P-type substrate and the N-type well are grounded. When a charge-up during a wiring layer etching has caused a positive voltage applied to the aforementioned N+ diffusion layer, the direction from the P-type well to the N-type well is a forward direction, and because the N-type well is grounded, it is possible to realize a diode having the N+ diffusion layer in the P-type well, assuring a current flow path. Moreover, when a charge-up during a wiring layer etching has caused a negative voltage applied to the aforementioned N+ diffusion layer, a direction from the N+ diffusion layer to the P-type well is a forward bias, thus enabling to realize a diode having the P-type well in the N-type well, assuring a current flow path.
Moreover, in a case when the charge-up preventing diode is connected to the control gate and during etching of a final wiring layer or the like, the control gate is cut off from the charge-up preventing diode, it is possible to assure a current flow path with the charge-up preventing diode and disconnection of the charge-up preventing diode by etching such as a final wiring layer etching enables to apply both of positive and negative voltages during a memory cell operation.